System level validation

V&V method implementation for the Validation of the IC at system level: -Test scenario to validate the interference in lab -Need to inject critical radar targets it in test bench, program 2/3 different targets to simulate critical scenario for self-interference -Capture and proceed the data for the scenario, run several times the scenario in order to characterize the repeatability of the measurement and extract any deviation. -Identify any ghost target, spurs for the tests -Link radar ghost targets to system and IC interference
UC3_TC_2
Functional
VALU3S Framework
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