NoC System Generator

Improved

The NoC System Generator(NSG) is developed by KTH. In the current version it is used to generate multicore NoC Systems on FPGAs. It can also make use of the Single-Event Mitigation (SEM) IP cores when targeting Xilinx FPGAs. KTH also has its own improved version of the SEM Core, called the KTH Healing Core. The Healing Core allows to Inject, Detect, and Correct Single and Multiple-Events on the FPGA.

The improved version of the tool will be able to a generate Virtual Prototype model of the NoC system for the Open Virtual Platform (OVP) provided by Imperas. The virtual protype will allow to simulate how faults injected into the SW binaries will affect the execution of the NoC System.

  • Öberg, J., Robino, F., “A NoC System Generator for the Sea-of-Cores Era”, In Proc. of FPGAWorld 2011, Copenhagen, Stockholm, Munich, September, 2011, ACM Digital Libraries.
  • F. Robino, J. Öberg, “The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA”, In Proc. of ReCoSoC-2013, Darmstadt, Germany, July 10-12, 2013.
  • F. Robino, J. Öberg, “From Simulink to NoC-based MPSoC on FPGA”, In proc. of DATE-2014, Dresden, Germany.
  • R. Seyyedi, M. T. Mohammadat, M. Fakih, K. Grüttner, J. Öberg and D. Graham, “Towards Virtual Prototyping of Synchronous Real-time Systems on NoC-based MPSoCs”, In Proc. of 12th IEEE International Symposium on Industrial Embedded Systems (SIES-2017),

Relationships with other web-repo artefacts
Improvement Classification
Reduced cost and time for work on certification process and functional safety
Open source - Goals
Yes
Safety, Functional Requirements
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