Improved Fault-injection on FPGAs

Virtual Prototypes allows to test and weed out potential SW bugs in advance, before the HW Platform has been built. This can be used to understand how faults propagate and manifest as errors at higher levels in a system.

Method Purpose Short description of the method's purpose and main benefits

To explore and evaluate the results of fault injection in an FPGA-based Hardware/Software Platform and its propagation to other system layers. To relate the fault injection on the low-level hardware layer to potential faults on the higher layers to reduce test space. The purpose of this Method is to generate a Digital Twin of the intended target architecture in UC10 to allow for early testing of its Software. The SW system will be exposed to Faults, by injecting bit-flips in the registers of the CPU models, and in stored data and in stored instructions in the memories.

Method description A detailed description of the method

A Virtual Prototype is generated of the intended Hardware, which allows to run the intended Software that will be part of the final System. In this way it allows for verification and validation of the Software before the Hardware is available. It can also be used to expose the SW system to Faults, by injecting Faults in the registers of the CPU models and in data and instructions stored in the memories.

Method Strengths A listof the strengths of the method

The advantage is that the system can be tested before the HW Platform has been built. This allows to weed out potential SW bugs in advance.

Method Limitations The limitations of the method

A virtual prototype is not always cycle-accurate.
Synchronizing between Multi-cores running SW in parallell is difficult. It requires that the synchronization points in the SW where the cores interact is well-defined.

Method References Bibliography references to papers about the method.

Open Virtual platforms - https://www.ovpworld.org/
QEMU - https://www.qemu.org/
Simics - https://www.windriver.com/products/simics
GEM5 - https://www.gem5.org/
NSG - NoC System Generator (https://github.com/Noctegra/NSG)
Xilinx Vivado tool suite (www.xilinx.com)
Vitis Unified Software Platform (https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html)

Method Dimensions

Evaluation Environment Type Type of environment where the method is applied. It can be more than one type of environment. (Dimension 1)

Evaluation Type Type of evaluation performed with that method. If a method is hybrid, more than one type can be selected. (Dimension 2)

Type of Component Under Evaluation Type of components that can be evaluated with that method. It can be more than one type. (Dimension 3)

Evaluation Stage The evaluation stage where the method is used. (Dimension 5)

Purpose of the Component Under Evaluation The type of purpose that can be evaluated by a method. It can be more than one type. (Dimension 6)

Type of Requirement Under Evaluation The type of requirements that a method is able to evaluate. It can be more than one type. (Dimension 7)

Evaluation Performance Indicator The type of evaluation criteria or KPI that a method is able to improve. It can be more than one type. (Dimension 8)

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