Processor Integration Verification within a System-Level Digital Twin of Legacy Systems

Processor Integration Verification within a System-Level Digital Twin of Legacy Systems is a method that supports determining the suitability of a new processor for a given system by the application of a digital twin.
This approach is an extension aligned to CPU Verification at Module-Level that shall improve overall situation. The method is based on the development of a digital twin that enables functional verification for a processor and thus gives an indication about the effort that is needed to verify the surrounding system. This enables a shift-left of the V&V activities in the product life-cycle (PLC) – issues are more likely found earlier.

Thorough verification of cyber-physical systems with CPUs is a high effort task. Once V&V is finished, the system will go operational in a product. However, a costly re-spin of verification might become necessary for several reasons such as the addition of new features that require more processing power, CPU parts that become unavailable due to electronic suppliers discontinuing production, components’ time of life, supply chain issues, or the evolution of components. This situation is tackled by relying on digital twins the ease the replacement of legacy components [CPUPIV-1].

Overall flow of the method:

  1. Implementation of a digital twin of the legacy system
  2. V&V of system behavior with digital twin including the legacy CPU model
  3. After successful V&V, replace the legacy CPU model with new one
  4. V&V of whole system with new CPU model
  5. If successful, the new CPU has similar behavior on system-level

After running this flow, following benefits should be gained:

  • Shift-left of the whole V&V process
  • When using unverified CPUs this method is an important first step for further deeper V&V activities.
  • Potential bugs can be found earlier.
  • An evaluation if the new CPU model works in an untimed environment.
  • Easy swap of CPU models (beneficial in cases of forced replacements of components and also for mere architecture exploration)
  • Indicates if system-wide changes are needed when changing CPU models.
  • Support for replacing CPU models on a digital twin
  • Early statement about a new CPU being suitable for the existing design
  • Shift-left in product life cycle and saving of costs
  • Potentially avoiding unnecessary costly V&V activities
  • Enables quicker response to market changes and supply chain issues
  • Only statements about a similar behaviour of a swapped CPU are feasible without full V&V

[CPUPIV-1] Santana, J., Pachiana, G., Markwirth, T., Sohrmann, C., Fischer, B., Matschning, M. (2022). Evaluating the feasibility of a RISC-V core for real-time applications using a virtual prototype, DVCon-US 2022.

Method Dimensions
In-the-lab environment
Experimental - Testing, Analytical - Formal, Experimental - Simulation
Hardware, Model
Integration testing, Unit testing, System testing
Thinking
Non-Functional - Safety, Non-Functional - Other, Functional, Non-Functional - Security
V&V process criteria, SCP criteria
Relations
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